The present invention relates to a semiconductor device, and more particularly, to a charge coupled device (CCD) having a CCIR/EIA mode conversion function.
Generally, for a CCD image sensor, there are a frame transfer mode, an interline transfer mode, and a frame interline transfer mode formed in combination with the aforementioned two modes, according to the reading mode of signal charges. The interline transfer mode is divided into an EIA (Electronic Industries Association) and CCIR (Consultative Committee International Radio) modes according to a scanning mode. FIGS. 1A and 1B show the optical black regions of the EIA and CCIR modes, respectively. In the EIA mode CCD having 250,000 pixels, effective pixels are 510(H).times.492(V), and its optical black region has the size of 25+2 horizontally (H) and 12+1 vertically (V). Accordingly, the total number of the pixels are 537(H).times.505(V). On the other hand, in the CCIR mode CCD having 290,000 pixels, effective pixels are 500(H).times.582(V), and its optical black region has the size of 30+7 horizontally (H) and 14+1 vertically (V). Accordingly, the total number of the pixels are 537(H).times.597(V).
FIGS. 2A and 2B are diagrams showing horizontal synchronous driving timings of the EIA and CCIR modes. In an EIA mode CCD, scanning is performed with 262(H) and 263(H) horizontal lines in even and odd fields for 1/60 seconds. In a CCIR mode CCD, scanning is performed with 312(H) and 313(H) horizontal lines in even and odd fields for 1/50 seconds. Accordingly, the vertical synchronous driving timings (not shown) of the EIA and CCIR modes are different from each other. Since the number of the effective pixels of the two modes in the horizontal lines are different from each other as shown in FIGS. 1A and 1B, their horizontal synchronous timings are also different from each other as shown in FIGS. 2A and 2B. In other words, the driving clock timings of the CCIR and EIA modes are different from each other.
In case that their driving timings are different from each other, if the driving clock timing of the CCIR mode is applied to the EIA mode, the timing is not enough for all the charges accumulated in the pixels of CCD used in the CCIR mode to be transmitted to a vertical charge transfer region. As a result, this affects image reproduction in CCD.
FIG. 3 is a layout of a conventional CCD. Referring to FIG. 3, gates are formed on a substrate which includes a plurality of photodiode (PD) regions, a plurality of vertical charge transfer (VCCD) regions for vertically transmitting image signal charges generated from the respective photodiodes, and a horizontal charge transfer region (HCCD) formed on one side of the VCCD region. That is, a plurality of first polysilicon gates 31 and second polysilicon gates 32 are alternately formed on the VCCD regions. First and second polysilicon gates 31 and 32 sequentially transmit the image signal charges generated from the photodiodes. Here, one side of second polysilicon gate 32 is formed to be superposed on the photodiode region, to be thereby used as a transfer gate.
In first and second polysilicon gates 31 and 32 formed on the VCCD region, a clock signal V.sub..phi.2 is applied to the first polysilicon gate 31, a clock signal V.sub..phi.1 to the second polysilicon gate 32, a clock signal V.sub..phi.4 to the next first polysilicon gate, and a clock signal V.sub..phi.3 to the next second polysilicon gate. By doing so, the first and second polysilicon gates transmit the image signal charges sequentially and vertically. That is, the transfer operation of the image signal charges is carried out in 4-phase clocking.
A plurality of first and second polysilicon gates 31a and 32a are formed on the HCCD region. First and second polysilicon gates 31a and 32a transmit the image signal charges, which are transmitted from the VCCD region in 2-phase clocking, to a sensing amplifier. This sensing amplifier converts the image signal charges into an image signal, what is output in turn. Clock signals H.sub..phi.1 and H.sub..phi.2 are alternately applied to first and second polysilicon gates 31a and 32a formed on the HCCD region. By doing so, first and second polysilicon gates 31a and 32a sequentially transfer the image signal charges.
As described above, in the conventional CCD, the potential level of the image signal charges generated from the respective pixel regions is changed according to the clock signals V.sub..phi.1, V.sub..phi.2, V.sub..phi.3, and V.sub..phi.4, and then the image signal charges are transmitted vertically. This image signal charges are transmitted to a floating gate region according to the clock signals H.sub..phi.1 and H.sub..phi.2 and converted into an analog signal through the sensing amplifier. The vertical and horizontal transfer of the image signal charges of the conventional CCD is carried out according to the respective transfer clock signals. However, in case that the CCIR mode CCD is used for the EIA mode, the driving clock timing of the EIA mode is faster than that of the CCIR mode. Accordingly, compared with the CCD used in the EIA mode, charges accumulated in many pixels of the CCD used for the CCIR mode cannot be transmitted to the VCCD regions. Here, the charges, which can not be transmitted to the VCCD region, are transmitted according to the next clock signal. These charges are overlapped with the charges of the previous pixel. As a result, images are overlapped with each other during image display.
The above-described conventional CCD has the following problems. Since the number of pixels of CCD according to the respective scanning modes are different from each other, one kind of CCD cannot be used in both EIA and CCIR modes. Accordingly, it is required that the CCD is changed according to its scanning mode.